1. Technical Field
The present invention is directed to a method and apparatus for optimum transparent latch placement in a macro based chip design.
2. Description of Related Art
Flip-flop style latches have the disadvantage of only capturing and passing data form input to output during a small transition period of the clock. That is, flip flop style latches only store the data of a data signal as when the clock signal goes high. This is known as a transition sensitive latch. As a result, if a data signal gets to the latch before the capturing transition of the clock, the data signal waits until the next capturing transition of the clock before it is latched and time is wasted. This is known as clock gating. If the data signal arrives after the clock capturing transition, then functionality of the circuit is broken.
When testability is not a large issue, flip-flop style latches may be replaced with transparent latches to make timing critical paths more efficient. Transparent latches are often known as level sensitive latches. This type of latch will pass data from input to output anytime while the clock is high. As a result, there is a larger timing window for data to pass from input to output with transparent latches and the transparent latch is less likely to be clock gated.
Large multi-cycle buses provide a case where testability is not a large issue and flip-flop style latches may be replaced with transparent latches. With large multi-cycle buses, i.e. buses that are large enough that more than one timing cycle is required to traverse the entire bus, cycles must be spent as the data traverses the bus. With such bus designs, once a floor plan has been established, the transparent latches of the bus must be placed such that the most timing critical signals are not clock gated during traversal, yet have sufficient slack and scalability. For large multi-cycle, multi-fanout buses, this is not a trivial problem.
Performing transparent latch placement by hand is a time consuming and error prone process. If a designer takes the time to perform manual transparent latch placement, the latches for large groups of bits are typically placed identically.
That is, a bus is a group of signals which are associated. Usually, a bus is carrying a binary number from one section of the chip to another. Individual signals of the bus then are sometimes called a bit because they are transporting one bit of the binary number. Because the signals are all associated, they originate from the same source, or portion of the chip (i.e. the same macro), and are destined for the same portion of the chip, or sink. Therefore, the signals all travel through the same macros from the source to the various sinks.
To simplify the design process the designer will group the bits of the bus together and treat them all the same. That is, all the latches for each of the bits will be placed in the same macros. However, due to topology it is often better to place the latches for certain bits in different macros. Furthermore, treating all of the bits the same may cause some bits to become unnecessarily timing critical.
Some placement tools have been devised for placement of transparent latches. These tools are generally referred to as “place and route tools” and work at an application specific integrated circuit (ASIC) level of the design. Examples of some of these tools include Cadence, Silicon, Ensemble and Synopsis. Most placement tools work on a smaller scale inside of individual macros, i.e. blocks of integrated circuit elements that together perform a designated function, and do not work on a large high performance macro based chip scale.
Thus, it would be beneficial to have an apparatus and method that automatically performs optimum transparent latch placement in a design at a chip level.